主题 : smart210进行ddr2内存初始化时,对其中的mrs进行配置时,整个程序卡死 复制链接 | 浏览器收藏 | 打印
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楼主  发表于: 2017-10-25 10:55

 smart210进行ddr2内存初始化时,对其中的mrs进行配置时,整个程序卡死

@****************************
@File:start.S
@
@±àD′èË£o′Ôòμí©
@****************************

.text
.global    _start
_start:
        b    reset                        
        ldr    pc, _undefined_instruction    
        ldr    pc, _software_interrupt        
        ldr    pc, _prefetch_abort            
        ldr    pc, _data_abort                
        ldr    pc, _not_used                
        ldr    pc, _irq                    
        ldr    pc, _fiq

_undefined_instruction: .word undefined_instruction
_software_interrupt:    .word software_interrupt
_prefetch_abort:    .word prefetch_abort
_data_abort:        .word data_abort
_not_used:        .word not_used
_irq:            .word irq
_fiq:            .word fiq                    

undefined_instruction:
        nop

software_interrupt:
        nop

prefetch_abort:
        nop

data_abort:
        nop

not_used:
        nop

irq:
        nop

fiq:
        nop

reset:
        bl set_svc
        bl disable_watchdog
        bl disable_interrupt
        bl disable_mmu
        bl init_clock
        bl mem_init
        bl light_led
        
        bl copy_to_ram
        bl stack_init
        bl bss_clean
        @ldr pc,=main
        
set_svc:
        mrs r0, cpsr
        bic r0, r0, #0x1f
        orr r0, r0, #0xd3
        msr cpsr, r0
        mov pc, lr

#define pWTCON 0xE2700000
disable_watchdog:
        ldr r0, =pWTCON
        mov r1, #0x0
        str r1, [r0]
        mov pc, lr

disable_interrupt:
    mvn r1,#0x0
    ldr r0,=0xf2000014
    str r1,[r0]

    ldr r0,=0xf2100014
    str r1,[r0]

    ldr r0,=0xf2200014
    str r1,[r0]

    ldr r0,=0xf2300014
    str r1,[r0]
    mov pc, lr

disable_mmu:
    mcr p15,0,r0,c7,c5,0
    mcr p15,0,r0,c7,c6,1
    mrc p15,0,r0,c1,c0,0
    bic r0, r0, #0x00000007
    mcr p15,0,r0,c1,c0,0
    mov pc, lr

#define CLK_DIV0 0xe0100300
#define MPLL_CON 0xe0100108
#define APLL_CON 0xe0100100
#define CLK_SRC  0xe0100200

#define DIV_VAL ((0x0<<0)|(4<<4)|(4<<8)|(1<<12)|(3<<16)|(1<<20)|(4<<24)|(1<<28))
#define APLL_VAL ((1<<31)|(3<<8)|(125<<16)|(1<<0))
#define MPLL_VAL ((1<<31)|(12<<8)|(667<<16)|(1<<0))

init_clock:
    ldr r0, =CLK_DIV0
    ldr r1, =DIV_VAL
    str r1, [r0]
    
    ldr r0, =APLL_CON
    ldr r1, =APLL_VAL
    str r1, [r0]
    
    ldr r0, =MPLL_CON
    ldr r1, =MPLL_VAL
    str r1, [r0]
    
    ldr r0, =CLK_SRC
    ldr r1, =0x1111
    str r1, [r0]
    
    mov pc, lr

stack_init:
    ldr sp,=0x24000000
    mov pc,lr

copy_to_ram:
    ldr r0, =0xd0020010
    ldr r1, =0x20008000
    add r2, r0, #1024*4
    
copy_loop:
    ldr r3,[r0],#4
    str r3,[r1],#4
    cmp r0,r2
    bne copy_loop
    mov pc,lr
    
bss_clean:
    ldr r0,=bss_start
    ldr r1,=bss_end
    cmp r0,r1
    moveq pc,lr

bss_clean_loop:
    mov r2,#0x0
    str r2,[r1],#4
    cmp r0,r1
    bne bss_clean_loop
    mov pc,lr

.global light_led
light_led:
    ldr    r0,=0xE0200280      
    mov    r1,#0x1
    str    r1,[r0]    
    ldr    r0,=0xE0200284
    mov    r1,#0x0
    str    r1,[r0]
    mov pc, lr



内存初始化程序
.text
.global mem_init
#define ELFIN_GPIO_BASE 0xE0200000
#define APB_DMC_0_BASE  0xF0000000
#define ASYNC_MSYS_DMC0_BASE        0xF1E00000

#define MP1_0DRV_SR_OFFSET         0x3CC
#define MP1_1DRV_SR_OFFSET         0x3EC
#define MP1_2DRV_SR_OFFSET         0x40C
#define MP1_3DRV_SR_OFFSET         0x42C
#define MP1_4DRV_SR_OFFSET         0x44C
#define MP1_5DRV_SR_OFFSET         0x46C
#define MP1_6DRV_SR_OFFSET         0x48C
#define MP1_7DRV_SR_OFFSET         0x4AC
#define MP1_8DRV_SR_OFFSET         0x4CC

#define DMC_CONCONTROL             0x00
#define DMC_MEMCONTROL             0x04
#define DMC_MEMCONFIG0             0x08
#define DMC_MEMCONFIG1             0x0C
#define DMC_DIRECTCMD             0x10
#define DMC_PRECHCONFIG         0x14
#define DMC_PHYCONTROL0         0x18
#define DMC_PHYCONTROL1         0x1C
#define DMC_RESERVED               0x20
#define DMC_PWRDNCONFIG         0x28
#define DMC_TIMINGAREF             0x30
#define DMC_TIMINGROW             0x34
#define DMC_TIMINGDATA             0x38
#define DMC_TIMINGPOWER         0x3C
#define DMC_PHYSTATUS             0x40
#define DMC_CHIP0STATUS         0x48
#define DMC_CHIP1STATUS         0x4C
#define DMC_AREFSTATUS             0x50
#define DMC_MRSTATUS               0x54
#define DMC_PHYTEST0               0x58
#define DMC_PHYTEST1               0x5C

#define DMC0_MEMCONTROL              0x00202400    // MemControl    BL=4, 1Chip, DDR2 Type, dynamic self refresh, force precharge, dynamic power down off
#define DMC0_MEMCONFIG_0          0x20E00323    // MemConfig0    256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
#define DMC0_MEMCONFIG_1          0x00E00323    // MemConfig1
#define DMC0_TIMINGA_REF        0x00000618      // TimingAref   7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)
#define DMC0_TIMING_ROW         0x2B34438A      // TimingRow    for @200MHz
#define DMC0_TIMING_DATA        0x24240000      // TimingData   CL=3
#define DMC0_TIMING_PWR         0x0BDC0343      // TimingPower
mem_init:
    /* DMC0 Drive Strength (Setting 2X) */

    ldr    r0, =ELFIN_GPIO_BASE

    ldr    r1, =0x0000AAAA
    str    r1, [r0, #MP1_0DRV_SR_OFFSET]

    ldr    r1, =0x0000AAAA
    str    r1, [r0, #MP1_1DRV_SR_OFFSET]

    ldr    r1, =0x0000AAAA
    str    r1, [r0, #MP1_2DRV_SR_OFFSET]

    ldr    r1, =0x0000AAAA
    str    r1, [r0, #MP1_3DRV_SR_OFFSET]

    ldr    r1, =0x0000AAAA
    str    r1, [r0, #MP1_4DRV_SR_OFFSET]

    ldr    r1, =0x0000AAAA
    str    r1, [r0, #MP1_5DRV_SR_OFFSET]

    ldr    r1, =0x0000AAAA
    str    r1, [r0, #MP1_6DRV_SR_OFFSET]

    ldr    r1, =0x0000AAAA
    str    r1, [r0, #MP1_7DRV_SR_OFFSET]

    ldr    r1, =0x00002AAA
    str    r1, [r0, #MP1_8DRV_SR_OFFSET]

    /* DMC0 initialization at single Type*/
    ldr    r0, =APB_DMC_0_BASE

    ldr    r1, =0x00101000                @PhyControl0 DLL parameter setting, manual 0x00101000
    str    r1, [r0, #DMC_PHYCONTROL0]

    ldr    r1, =0x00000086                @PhyControl1 DLL parameter setting, LPDDR/LPDDR2 Case
    str    r1, [r0, #DMC_PHYCONTROL1]

    ldr    r1, =0x00101002                @PhyControl0 DLL on
    str    r1, [r0, #DMC_PHYCONTROL0]

    ldr    r1, =0x00101003                @PhyControl0 DLL start
    str    r1, [r0, #DMC_PHYCONTROL0]

find_lock_val:
    ldr    r1, [r0, #DMC_PHYSTATUS]        @Load Phystatus register value
    and    r2, r1, #0x7
    cmp    r2, #0x7                @Loop until DLL is locked
    bne    find_lock_val

    and    r1, #0x3fc0
    mov    r2, r1, LSL #18
    orr    r2, r2, #0x100000
    orr    r2 ,r2, #0x1000

    orr    r1, r2, #0x3                @Force Value locking
    str    r1, [r0, #DMC_PHYCONTROL0]

#if 0    /* Memory margin test 10.01.05 */
    orr    r1, r2, #0x1                @DLL off
    str    r1, [r0, #DMC_PHYCONTROL0]
#endif
    /* setting DDR2 */
    ldr    r1, =0x0FFF2010                @ConControl auto refresh off
    str    r1, [r0, #DMC_CONCONTROL]

    ldr    r1, =DMC0_MEMCONTROL            @MemControl BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
    str    r1, [r0, #DMC_MEMCONTROL]

    ldr    r1, =DMC0_MEMCONFIG_0            @MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
    str    r1, [r0, #DMC_MEMCONFIG0]

    ldr    r1, =DMC0_MEMCONFIG_1            @MemConfig1
    str    r1, [r0, #DMC_MEMCONFIG1]

    ldr    r1, =0xFF000000                @PrechConfig
    str    r1, [r0, #DMC_PRECHCONFIG]

    ldr    r1, =DMC0_TIMINGA_REF            @TimingAref    7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)
    str    r1, [r0, #DMC_TIMINGAREF]

    ldr    r1, =DMC0_TIMING_ROW            @TimingRow    for @200MHz
    str    r1, [r0, #DMC_TIMINGROW]

    ldr    r1, =DMC0_TIMING_DATA            @TimingData    CL=4
    str    r1, [r0, #DMC_TIMINGDATA]

    ldr    r1, =DMC0_TIMING_PWR            @TimingPower
    str    r1, [r0, #DMC_TIMINGPOWER]

    ldr    r1, =0x07000000                @DirectCmd    chip0 Deselect
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x01000000                @DirectCmd    chip0 PALL
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00020000                @DirectCmd    chip0 EMRS2
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00030000                @DirectCmd    chip0 EMRS3
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00010400                @DirectCmd    chip0 EMRS1 (MEM DLL on, DQS# disable)
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00000542                @DirectCmd    chip0 MRS (MEM DLL reset) CL=4, BL=4

    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x01000000                @DirectCmd    chip0 PALL
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x05000000                @DirectCmd    chip0 REFA
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x05000000                @DirectCmd    chip0 REFA
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00000442                @DirectCmd    chip0 MRS (MEM DLL unreset)
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00010780                @DirectCmd    chip0 EMRS1 (OCD default)
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00010400                @DirectCmd    chip0 EMRS1 (OCD exit)
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x07100000                @DirectCmd    chip1 Deselect
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x01100000                @DirectCmd    chip1 PALL
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00120000                @DirectCmd    chip1 EMRS2
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00130000                @DirectCmd    chip1 EMRS3
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00110400                @DirectCmd    chip1 EMRS1 (MEM DLL on, DQS# disable)
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00100542                @DirectCmd    chip1 MRS (MEM DLL reset) CL=4, BL=4
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x01100000                @DirectCmd    chip1 PALL
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x05100000                @DirectCmd    chip1 REFA
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x05100000                @DirectCmd    chip1 REFA
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00100442                @DirectCmd    chip1 MRS (MEM DLL unreset)
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00110780                @DirectCmd    chip1 EMRS1 (OCD default)
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x00110400                @DirectCmd    chip1 EMRS1 (OCD exit)
    str    r1, [r0, #DMC_DIRECTCMD]

    ldr    r1, =0x0FF02030                @ConControl    auto refresh on
    str    r1, [r0, #DMC_CONCONTROL]

    ldr    r1, =0xFFFF00FF                @PwrdnConfig
    str    r1, [r0, #DMC_PWRDNCONFIG]

    ldr    r1, =0x00202400                @MemControl    BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
    str    r1, [r0, #DMC_MEMCONTROL]

    mov pc,lr